A comprehensive modeling approach for the task mapping problem in heterogeneous systems with dataflow processing units

Summary We introduce a new model for the task mapping problem to aid in systematic design of algorithms heterogeneous systems including, but not limited to, CPUs, GPUs, and FPGAs. A special focus is set on communication between devices, its influence parallel execution, as well device‐specific differences regarding parallelizability streamability. give comprehensive description how given can be abstractly evaluated including mappings dataflow‐based hardware accelerators. show this utilized different system phases present two novel mixed‐integer linear programs demonstrate usage model, showing significant improvements compared pure CPU randomly generated graphs. To best our knowledge, we first ILP that considers pipelining effects when streaming tasks an FPGA.